This invention relates to digital signal processing microchips (DSP's) and more particularly to the architecture of a digital signal processor embodied in a single very large scale integrated silicon chip (VLSI) which is capable of conducting adapative differential pulse code modulation (ADPCM) telecommunication algorithms.
Digital signal processors have been known in the art for some time. (See e.g., L. Robert Morris, "Digital Signal Processing Microprocessors: Forward to the Past?" IEEE MICRO, Vol. 6, No. 6, pp. 6-8, December 1986). Typically they are high speed reduced instruction set devices which are capable of carrying out limited tasks such as addition, subtraction, multiplication, division, and shifting operations in a much quicker time frame then the slower, more powerful microprocessors. The DSP's of the art typically include a microinstruction sequencer (MIS) including a read only memory (ROM), a random access memory RAM, an arithmetic-logic unit (ALU), a high speed multiplier, and related storage registers. The MIS typically acts to control the functioning of the DSP. The ALU typically performs arithmetic and logic functions under the control of the DSP. The RAM is used to store values which are sent to the DSP from circuitry exterior to the DSP as well as values which are computed by the ALU or directly generated in the ROM of the MIS. The registers are typically used as input or output storage for each of the elements of the DSP.
While the combination of a MIS, a RAM, a multiplier, and an ALU in a DSP permit a DSP to perform a wide range of functions in an efficient manner, it will be appreciated that complex algorithms such as the ADPCM algorithm are not as easily accommodated by such an arrangement. Indeed, in attempting to perform the ADPCM algorithm with the DSP's of the art, several DSP's have had to be utilized.